module dual_port_RAM_2cyc #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk	,
	 input wenc	,
	 input [$clog2(DEPTH)-1:0] waddr	,
	 input [WIDTH-1:0] wdata	,
	 input rclk	,
	 input renc	,
	 input [$clog2(DEPTH)-1:0] raddr	,
	 output reg [WIDTH-1:0] rdata
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

reg [WIDTH-1:0] wdata_ff;
always @(posedge wclk) begin
	if(wenc)begin
		RAM_MEM[waddr] <= wdata_ff;
    end
    wdata_ff <= wdata;
end 

reg [WIDTH-1:0] rdata_ff;
always @(posedge rclk) begin
	if(renc) begin
		rdata_ff <= RAM_MEM[raddr];
    end
    rdata    <= rdata_ff;
end 

endmodule  
